1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly to a memory block replacement system and replacement method for a semiconductor memory constituted by an electrically erasable and programmable read-only memory (EEPROM).
1. Description of the Related Art
In semiconductor memories, a reduction in the yield and an increase in the test cost are recently becoming an important problem, as the memory capacitance and the circuit scale are enlarged.
As a solution method for the reduction in yield, there is a method which enhances yield by replacing a defective memory with a redundancy memory. As one of the replacement methods there is a block switching method. This method is equipped with a redundancy memory block in addition to normal memory blocks. When a defective memory cell is present within a normal memory block, the defective memory block is replaced with a redundancy memory block. Since this method performs replacement at a block unit, it has the advantage that a circuit for replacement is structurally simple as compared with a method such as word line replacement, bit line replacement, etc.
As a solution method for the increase in test cost, there is a method in which a ROM incorporating a specific program therein is previously provided in circuitry. This specific program is used to confirm if memory or peripheral circuitry operates correctly. If this program is used, an efficient operational test will become possible and an increase in the test cost can be suppressed. Here, the ROM incorporating this specific program is referred to as the test ROM.
FIG. 6 shows a conventional semiconductor memory of the above kind. The semiconductor memory consists of main memory blocks 11 to 14, a redundancy memory block 10, a test ROM 15, and a control section 16 for controlling these.
Now, in the case where the main memory blocks 11 to 14 are normal, the redundancy memory block 10 is not used.
On the other hand, when a defective memory cell is present in any of the main memory blocks 11 to 14, the main memory block having the defective memory cell (any of 11 to 14) is exchanged for the redundancy memory block 10 by the control section 16.
The control section 16 also tests the main memory blocks 11 to 14, redundancy memory block 10, and other semiconductor memory circuits by employing a test program written within the test ROM 15.
Another semiconductor memory of the above type is described in Japanese Patent Application Laid-Open No. 3-104097. In the case where this semiconductor memory has a plurality of redundancy circuits, when there is a defect in one redundancy circuit, the semiconductor memory causes the one redundancy circuit to be in an unusable state.
However, in the method of providing a redundancy memory block, even when only one portion in a memory block, for example, a single memory cell is defective, the block is replaced for relief. For this reason, although the other memory cells within the block operate correctly, they are not used and therefore there is a disadvantage that the memory utilization efficiency is low.
Also, providing the test ROM results in an increase in the memory area, and furthermore, in the case where a defective memory is present within the test ROM, there is a disadvantage that there is no relief means.
Moreover, the semiconductor memory of the aforementioned Japanese Patent Application Laid-Open No. 3-104097 does not describe a means of overcoming this disadvantage.